With the sharp increase in semiconductor equipment integration, the MOS transistors tend to be more miniaturized.
FIGS. 1 (a) and (b) show a top view and a sectional view, respectively, for a conventional MOS transistor structure. The conventional MOS transistor consists of the following elements:
1. Gate electrode 4, formed on the device field of semiconductor substrate 1 through gate oxide layer 3; PA0 2. Source region and drain region 8; and PA0 3. Contacting electrode 11, formed to connect to the source region and drain region 8.
In addition, the MOS transistor shown in FIG. 1 is equipped with a wiring layer 12 to connect to a contacting electrode 11. The wiring layer 12, the contacting electrode 11, and the gate electrode 4 are electrically isolated by an interlayer insulating layer 9. The source region and drain region 8 consist of the following elements:
The first diffusion layer 6, formed by diffusing impurities on the device field surface other than the gate electrode 4, and the second diffusion layer 8, formed by diffusing impurities on the device field surface other than the region, where an insulating layer 7 formed on the side-wall of the gate electrode 4 is grown. The source region and drain region 8 are referred to as Lightly Doped Drain structure for the above structure.
In a conventional MOS transistor having such a structure, it is required to increase the separation between the contacting electrode 11 and the gate electrode 4, in order to prevent short-circuiting between two electrodes. Accordingly, the MOS transistor needs a larger proportion of the surface area compared to the whole semiconductor equipment. Therefore, it is impossible to achieve higher semiconductor equipment integration. Furthermore, the separation between the contacting electrode 11 and the gate electrode 4 is so large that it increases the parasitic resistance due to the source region or drain region 8. As transistors are being miniaturized, resistance of the channel region decreases. Thus, the proportion of the parasitic resistance to the resistance of the channel region increases. In other words, the above parasitic resistance causes unusual deterioration in the drive power for transistors.
To solve the aforesaid problems, the position of the contacting electrode 11 is aligned to the gate electrode 4 in the semiconductor equipment shown in FIG. 2. This structure is referred to as SAC (Self Align Contact) structure. FIG. 2 (a) shows a top view and (b) shows a sectional view, respectively, for MOS transistors having the SAC structure. The insulating layer 5 and the side-wall insulating layer 7 cover the gate electrode 4 to prevent short-circuiting between the contacting electrode 11 and the gate electrode 4.
FIG. 3 shows a sectional view for a method to manufacture the MOS transistor having the SAC structure. The gate insulating layer 3, the gate electrode 4, and the insulating layer 5 are formed in sequence on the semiconductor substrate 1, where a device isolation field 2 was formed. Thereafter, the first diffusion layer 6 is formed on a portion other than this gate electrode 4 and this insulating layer 5, using the ion implantation method. (FIG. 3 (a))
Next, for example, insulating layers are stacked so as to cover the gate electrode 4. After the insulating layers are formed, the insulating layers on the semiconductor substrate 1 are removed, using the anisotropic etching method, thereby forming the insulating layer 7 on the side-wall of the gate electrode 4. Further, the second diffusion layer 8 can be formed, for instance, using the ion implantation method. (FIG. 3(b))
Thereafter, the interlayer insulating layer 9 is formed over the entire surface of semiconductor substrate 1. Further, contacting holes 10a and 10b are opened within the interlayer insulating layer 9 by the normal lithography technique and the anisotropic etching method (FIG. 3(c)). At this time, the anisotropic etching should be performed under the condition where an etching speed to the insulating layers 5 and 7 is slower than that to the interlayer insulating layer 9. This enables the insulating layers 5 and 7 to remain, as shown in FIG. 3(c). Therefore, there is no need to increase the separation between the contacting holes 10a, 10b, and the gate electrode 4, even if an overlay offset (an overlay offset between predetermined clearance region of the contacting holes 10a and 10b, and the actual clearance region) occurs.
Subsequently, the contacting electrode 11 is formed by embedding tungsten etc. into the contacting holes 10a and 10b. Wiring 12 is formed on the upper area of the contacting electrode 11 by using Al, etc., thereby producing the MOS transistor, as shown in FIG. 2 (b).
As described above, the conventional MOS transistor having the SAC structure can reduce the separation between the contacting holes 10a/10b and the electrode 4, which can miniaturize the MOS transistor. On the other hand, the separation between the channel region and the contacting electrode 11 of the MOS transistor is shortened, so that the parasitic resistance can be reduced. Particularly, as shown in FIG. 2 (a), the pattern for the contacting hole 10 is formed so as to overlap with the gate electrode 4 pattern, which enables the separation between the channel region and the contacting electrode 11 to be equal to the width of side-wall insulating layer 7. Therefore, the parasitic resistance, due to the source region or drain region 8, can be miniaturized.
Meanwhile, in order to minimize the parasitic resistance, as described above, it is required to overlay the connecting holes 10a, 10b and the gate electrode 4 each other, as shown in FIG. 2 (a), by at least overlay offset separation b for the aforesaid contacting holes 10a and 10b. At this time, the separation c between the contacting holes 10a and 10b is expressed by Equation: c=d-2.times.b, in the case when the gate electrode 4 width is specified at d.
Generally, many cases used to miniaturize the transistor provide the width for the gate electrode 4 with a critical minimum size, so that the gate electrode pattern can be formed. Therefore, the separation between the contacting holes 10a and 10b will be shorter than a critical minimum size for fabrication of gate electrode, which makes it very difficult to simultaneously pattern the contacting holes 10a and 10b. assuming discretely patterning the contacting holes 10a and 10b, a problem will occur in which the number of manufacturing processes increase. Furthermore, it can not be assured that the cross section of the interlayer insulating layer 9, between the contacting holes 10a and 10b, appears in a rectangular shape, as shown in FIG. 2 (b), which causes to short the contacting electrodes 11a and 11b formed inside of the holes 10a and 10b. Thus, it is necessary to take new measures to avoid the aforesaid problems.
As described above, the conventional manufacturing method used for semiconductor equipment was found to make it difficult to simultaneously align predetermined contacting holes located at both ends of the gate electrode for the gate electrode.